module main_dec(
    input wire [5:0] op,
    output wire regwrite,regdst,alusrc,branch,memwrite,memetoreg,jump,
    output wire[1:0] aluop
);
reg[1:0] aluop_reg ;
reg[8:0] sigs ;



assign {regwrite,regdst,alusrc,branch,memwrite,memetoreg,jump,aluop} = sigs;
always @(*) begin
  case(op)
    6'b000000:begin    //R-type  
      sigs      <= 9'b110000010;
    end
    6'b100011:begin  // lw
       sigs      <= 9'b101001000;
    end
    6'b101011:begin   //sw
       sigs      <= 9'b001010000;
    end
    6'b000100:begin   //beq
      sigs      <= 9'b00100001;
    end
    6'b001000:begin   //addi
       sigs      <= 9'b101000000;
    end
    6'b000010:begin   //j
       sigs      <= 9'b000000100;
    end
    default: begin
        sigs      <= 9'bxxxxxxxxx;
    end

endcase
end

endmodule

module alu_dec(
    input wire [5:0] funct,
    input wire [1:0] aluop,
    output wire [2:0] alucontrol
);

assign alucontrol = (aluop == 2'b00)?3'b010:
                     (aluop == 2'b01)?3'b110:
                     (aluop == 2'b10)?
                            (funct == 6'b100000)? 3'b010: //+ - and or
                            (funct == 6'b100010)? 3'b110:
                            (funct == 6'b100100)? 3'b000:
                            (funct == 6'b100101)? 3'b001:
                            (funct == 6'b101010)? 3'b111:
                            3'b000 : 3'bxxx;
endmodule

module controller(
    input wire [31:0] instr,
    output wire jump,regwrite,regdst,alusrc,branch,memwrite,memetoreg,
    output wire [2:0] alucontrol
);
wire[1:0] aluop ;

main_dec main_dec(
    .op(instr[31:26]),
    .jump(jump),
    .branch(branch),
    .alusrc(alusrc),
    .memwrite(memwrite),
    .memetoreg(memetoreg),
    .regwrite(regwrite),
    .regdst(regdst),
    .aluop(aluop)

);

alu_dec alu_dec(
    .funct(instr[5:0]),
    .aluop(aluop),
    .alucontrol(alucontrol)
);
endmodule